Linus Torvalds writes: (Summary) Of
course all those features are enabled.
course all those features are enabled.
That's weak even by modern standards.
I have MPX bounds and MPX CSR on my old Skylake.
I have MPX bounds and MPX CSR on my old Skylake.
And the real worry is things like AVX-512 etc, which is exactly when things like "save and restore one ymm register" will quite likely clear the upper bits of the zmm register.
clear the upper bits of the zmm register.
And yes, we can have some statically patched code that takes that into account, and saves the whole zmm register when AVX512 is on, but the whole *point* of the dynamic XSAVES thing is actually that Intel wants to be able enable new user-space features without having to wait for OS support.
course all those features are enabled.
[...]
Note that this is with an AVX (128-bit) supporting CPU: That's weak even by modern standards.That's weak even by modern standards.
I have MPX bounds and MPX CSR on my old Skylake.
I have MPX bounds and MPX CSR on my old Skylake.
And the real worry is things like AVX-512 etc, which is exactly when things like "save and restore one ymm register" will quite likely clear the upper bits of the zmm register.
clear the upper bits of the zmm register.
And yes, we can have some statically patched code that takes that into account, and saves the whole zmm register when AVX512 is on, but the whole *point* of the dynamic XSAVES thing is actually that Intel wants to be able enable new user-space features without having to wait for OS support.