Linus Torvalds writes: (Summary) wrote:
Afaik, x86 will not cache PCI unless the system is misconfigured, and even then it's more likely to just raise a machine check exception than cache things.
than cache things.
The last-level cache is going to do fills and spills directly to the memory controller, not to the PCIe side of things.
memory controller, not to the PCIe side of things.
(I guess you *can* do things differently, and I wouldn't be surprised if some people inside Intel did try to do things differently with trying nvram over PCIe, but in general I think the above is true) trying nvram over PCIe, but in general I think the above is true) You won't find it in the kernel code either.
[...]
untangle the code :-)Afaik, x86 will not cache PCI unless the system is misconfigured, and even then it's more likely to just raise a machine check exception than cache things.
than cache things.
The last-level cache is going to do fills and spills directly to the memory controller, not to the PCIe side of things.
memory controller, not to the PCIe side of things.
(I guess you *can* do things differently, and I wouldn't be surprised if some people inside Intel did try to do things differently with trying nvram over PCIe, but in general I think the above is true) trying nvram over PCIe, but in general I think the above is true) You won't find it in the kernel code either.